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Third IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits held in conjunction with ITC / Test Week 2012 |
CALL
FOR PAPERS |
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Scope | |
The 3D-TEST Workshop focuses exclusively on test of and design-for-test for three-dimensional stacked ICs (3D-SICs), including Systems-in-Package (SiP), Package-on-Package (PoP), and especially 3D-SICs based on Through-Silicon Vias (TSVs). While 3D-SICs offer many attractive advantages with respect to heterogeneous integration, smaller form-factor, higher bandwidth and performance, and lower power dissipation, there are many open issues with respect to testing such products. The 3D-TEST Workshop offers a forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike. 3D-TEST will take place in conjunction with the IEEE International Test Conference (ITC) and is sponsored by the Test Technology Technical Council (TTTC) of IEEE Computer Society. Topic Areas – You are invited to participate and submit your contributions to the 3D-TEST Workshop. The workshop’s areas of interest include (but are not limited to) the following topics:
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Submissions | |
Submission Instructions – Submissions must be sent in as PDF file. The Workshop prefers Full Paper submissions (of up to six pages), but also allows Extended Abstract submissions (of at least two pages). Detailed submission instructions can be found at the Workshop’s website: http://3dtest.tttc-events.org. All submissions will be evaluated for selection with respect to their suitability for the workshop, originality, technical soundness, and presented results. Selected submissions can be accepted for regular or poster presentation at the Workshop. Publications – The workshop will make available to all participants an Electronic Workshop Digest, which includes all material that authors are willing to provide: abstract, paper, slides, poster, etc. |
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Key Dates | |
Submission deadline: September 7, 2012 |
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Additional Information | |
Further InformationYervant Zorian Erik Jan Marinissen Said Hamdioui | |
Committees | |
General Chair: Program Chairs: Finance Chair: Publication Chair: Publicity Chair: Web Chair: Arrangements Chair: Program Committee Members:
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For
more information, visit us on the web at: http://3dtest.tttc-events.org |
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The Third IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-Test 2012) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC). |
IEEE
Computer Society- Test Technology Technical Council |
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TTTC
CHAIR PAST
CHAIR TTTC
1ST VICE CHAIR SECRETARY ITC GENERAL CHAIR TEST
WEEK COORDINATOR TUTORIALS
AND EDUCATION STANDARDS EUROPE MIDDLE
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COMMITTEES ELECTRONIC
MEDIA |
PRESIDENT OF BOARD SENIOR
PAST CHAIR TTTC 2ND VICE CHAIR FINANCE IEEE DESIGN & TEST EIC TECHNICAL
MEETINGS TECHNICAL
ACTIVITIES ASIA
& PACIFIC LATIN
AMERICA NORTH
AMERICA COMMUNICATIONS INDUSTRY
ADVISORY BOARD |